In the design of a mainframe CPU, it is highly desirable to provide powerful and reliable error detection and handling features, and this requirement has mandated the provision of various circuits, firmware and software to sense and resolve the diverse types of errors which may occur in operation. When a fault is sensed, it is often necessary to abort an operation in process since the result cannot be trusted. If the fault source is corrected, or if it is determined to have been the result of a transient condition, processing may be resumed, but must do so at a point in the processing operation prior to the operation which resulted in the fault. Thus, it is well known to provide for the temporary storage of a "safestore frame" which contains the essential information necessary to effect a resumption of processing. This essential information typically includes the results of the execution of an ascertainable instruction preceding the fault and may include supplementary information such as the contents of various registers in the processing unit at that time.
In one CPU configuration in which the present invention finds use, certain chips in a Basic Processing Unit (BPU) are provided in master/slave pairs with the results of data manipulation in the BPU being compared for identity. During the data manipulation, safestore information (e.g., the software visible registers in the chips which are active in the current operation) is accessible on master and slave result busses which also serve to supply the execution results from each instruction for comparison to error sensing circuitry. Consequently, there is the opportunity, after the occurrence of a fault and a decision to resume, to return execution to the same or a different CPU at an operation point immediately preceding that at which the fault was sensed.